Warp Instruction Pipeline Hazard Simulator

Simulating GPU warp pipeline hazards and operand forwarding

This hard coding problem tests your ability to model a real hardware execution pipeline—specifically the 5-stage instruction pipeline that NVIDIA GPUs use to execute warps. It requires you to track data dependencies, compute stall cycles correctly under two different forwarding policies, and handle edge cases in register hazard detection.

The core challenge is distinguishing between Read-After-Write (RAW) hazards under two scenarios: without forwarding, where a consumer must wait for the producer's write-back stage; and with forwarding, where results can be fed directly between stages, but load-use hazards still incur a one-cycle penalty. You'll need to track when each instruction occupies each pipeline stage, identify which source registers depend on prior writes, compute the stall cost for each dependency based on instruction distance and forwarding capability, and accumulate the maximum stall at each decision point.

• Pipeline stage timing and instruction latencies
• Data hazard detection and dependency tracking
• Operand forwarding paths (ALU vs. load results)
• Stall calculation and critical-path reasoning
• Write-first semantics in the register file