Streaming Median
What this preview is
Streaming Median is a hard quant coding problem on digital design in System Verilog.
- Difficulty
- Hard
- Topic
- Digital Design
- Discipline
- Quant hardware engineering
- Language
- System Verilog
Designing a streaming sliding-window median calculator in SystemVerilog
This hard hardware design problem tests whether you can implement a real-time statistical operator on streaming data—a common requirement in financial signal processing and market-data pipelines. You must maintain a fixed-size window, sort or track order dynamically, and emit results every cycle once the window fills, all while respecting AXI-Stream handshake semantics and clock-by-clock timing.
The core challenge is choosing an efficient data structure and sorting strategy. A naive approach (storing 7 elements and fully sorting every cycle) works but may not meet latency or area constraints. Strong solutions consider trade-offs between insertion-order tracking, partial sorting, or specialized median-finding algorithms. You must also handle the stream protocol correctly: buffer incoming data only when i_data_valid is asserted, emit median only after 7 valid elements arrive, and reset state cleanly when i_data_last marks the end of a stream segment.
- Circular buffers and window management
- Sorting networks vs. insertion-sort vs. heap-based selection
- Pipelining and throughput: one result per input cycle after warm-up
- AXI-Stream protocol: valid/ready/last handshaking
- Synchronous reset and edge-case handling (short streams, back-to-back streams)
Unlock full access to getcracked
Join to unlock this problem, detailed solutions, and our complete library of quant finance interview prep.