Streaming Buffer

Streaming buffer with byte-wise write and variable-length read in SystemVerilog

This is a hard digital-design coding problem that tests your ability to build a practical, synthesizable storage interface in SystemVerilog. You will implement a 1024-byte addressable memory with independent write-enable control per byte lane and a high-throughput streaming read path that can deliver up to four valid bytes per cycle, regardless of alignment or request size.

The challenge lies in managing the asymmetry between write (32-bit granule, FIFO-style sequential packing) and read (arbitrary byte address, variable length, streaming output with per-byte validity flags) operations. You must handle edge cases such as unaligned reads, partial writes, and the coordination between write and read pointers in a single clock domain. Strong solutions clearly separate the memory storage, write logic with byte-enable decoding, and read logic with output slicing and validity generation.

• FIFO-style sequential write with per-byte-lane enable signals
• Arbitrary-address, variable-length streaming reads
• Per-byte output validity (TVALID as 4-bit mask)
• Unaligned read support and read-pointer auto-increment
• Clock-domain synchronization and reset handling