APB Master
What this preview is
APB Master is a medium quant coding problem on digital design in System Verilog.
- Difficulty
- Medium
- Topic
- Digital Design
- Discipline
- Quant hardware engineering
- Language
- System Verilog
Designing a synthesisable APB master controller in SystemVerilog
This medium-difficulty digital design problem asks you to build a complete APB (Advanced Peripheral Bus) master interface using a finite state machine. It tests whether you can translate a protocol specification into synthesisable SystemVerilog while managing handshaking, state transitions, and data flow control.
The core challenge is implementing a multi-state FSM that respects APB timing rules: initiating transactions on command, holding address and control signals stable during the access phase, capturing slave responses at the right cycle, and chaining operations (reading data, incrementing it, then writing it back). You must also handle wait states gracefully when the slave is not ready, and maintain proper synchronous reset discipline throughout.
- Finite state machine design and state encoding
- Protocol handshaking and ready/valid signalling
- Combinational vs. sequential logic for address and data paths
- Data capture and pipeline ordering across clock cycles
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