AXI Master
What this preview is
AXI Master is a medium quant coding problem on digital design in System Verilog.
- Difficulty
- Medium
- Topic
- Digital Design
- Discipline
- Quant hardware engineering
- Language
- System Verilog
Designing and verifying an AXI4-Lite master controller in SystemVerilog
This medium-difficulty hardware design problem asks you to build a synthesizable AXI4-Lite master interface using a finite state machine. It is representative of the digital-design rounds at semiconductor and FPGA firms, where protocol compliance, correct handshaking, and clean state management all matter equally.
The core challenge is managing the AXI4-Lite protocol's five independent channels—each with its own VALID/READY handshake—while orchestrating a sequence of read and write operations. Unlike simpler bus protocols, AXI4-Lite decouples the write address and write data channels, so they can complete their transfers independently; your FSM must track and coordinate both paths correctly. You must also handle wait states gracefully, keep signals stable according to the protocol rules, and capture data only when a handshake completes.
- Finite state machine design for multi-channel synchronization
- AXI4-Lite handshake protocol and signal stability rules
- Independent address and data channel orchestration
- Data capture and manipulation across transaction sequences
- Response checking and error handling