Divisible by n

Building a serial divisibility detector in SystemVerilog

This medium-difficulty digital design problem asks you to implement a sequential circuit that tracks divisibility of a continuously received binary stream. It combines synchronous state management with modular arithmetic—a common pattern in hardware interview rounds at firms working with streaming data or signal processing.

The core challenge is updating a divisibility check one bit at a time without reconstructing the entire accumulated number. You must latch a divisor value on reset, then process each incoming bit while maintaining only the information necessary to determine whether the current cumulative value is divisible by N. The key insight is that when you shift left and append a new bit, the remainder modulo N evolves in a predictable way—allowing you to track divisibility without storing arbitrarily large values.

• Modular arithmetic and remainder propagation
• Synchronous state machines and reset semantics
• Bit-serial data processing and shift operations
• Latching external parameters during reset