Clock that bus!

Crossing asynchronous clock domains with multi-bit data

This is a medium-difficulty digital design question that tests your understanding of clock domain crossing (CDC) and the practical constraints of synchronising multi-bit signals across unrelated clock domains. It is a common topic in FPGA and ASIC interview loops, especially for roles involving hardware design or verification.

The core challenge is that when data must move between clock domains operating at different frequencies or phases, simple flip-flop synchronisers fail for bus-width signals because different bits may be sampled at different times, creating metastability risk and the potential for data corruption. The question asks you to reason about synchronisation constructs suited to scenarios where bandwidth and latency are not critical—such as control signals or low-frequency register writes—rather than high-throughput streaming data.

• Metastability and synchroniser design
• Gray code encoding for multi-bit CDC
• CDC protocols and handshake mechanisms
• Trade-offs between latency, throughput, and complexity