How large can you Mux?

What this FPGA multiplexer design question tests

This is a fundamental digital-design problem that quant and trading-systems engineers encounter when optimizing FPGA implementations for low-latency signal processing and market data pipelines. It probes whether you understand the relationship between lookup-table capacity and combinational logic synthesis.

To solve it, you need to reason about how a k-input LUT can be configured to implement arbitrary Boolean functions, and specifically how many address lines a multiplexer requires relative to the LUT's input width. The question rewards clear thinking about the trade-off between the selector width and the number of distinct data inputs that can be routed through a single primitive.

• LUT as a function generator and memory element
• Multiplexer encoding and selector bits
• Mapping combinational logic to FPGA fabric