A unique case

What this SystemVerilog unique case synthesis question tests

This is an easy digital-design question that probes understanding of how the unique case statement in SystemVerilog guides synthesis optimizations. It rewards knowing the contract between the designer and the synthesis tool: when you declare a case unique, you promise that only one branch will ever match, allowing the tool to eliminate redundant logic and save area.

The question tests whether you understand what happens when that promise is broken—specifically, when multiple case conditions could simultaneously be true. Candidates need to reason about the difference between simulation semantics (what the code actually does) and synthesis semantics (what the tool assumes based on your declarations), and recognize that violating a unique constraint can lead to unexpected behavior or tool warnings.

• Synthesis directives and their runtime implications
• One-hot encoding and multiplexer design patterns
• The cost of over-constraining designs