Tick that price

What this FPGA tick-calculation interview question tests

This is a medium-difficulty digital-design problem that asks you to implement a tick calculator in an FPGA context. It probes your ability to translate a market-microstructure concept—measuring price displacement from a reference point in discrete tick units—into hardware logic.

The core challenge is working with fixed-point arithmetic, handling signed arithmetic correctly, and reasoning about the precision and rounding behaviour required when converting a continuous price difference into a tick count. Firms designing low-latency trading systems care about whether you understand the data-path constraints, how to avoid unnecessary complexity in hardware, and how to make design choices that preserve accuracy while meeting timing closure.

• Fixed-point number representation and scaling
• Division and rounding in hardware (especially with non-power-of-two divisors)
• Signed arithmetic and overflow handling
• Pipelining and latency trade-offs in market-data processing