Always use your comb

Understanding combinational logic in SystemVerilog

This is a medium-difficulty digital design question that tests your grasp of the subtle but important distinctions between SystemVerilog's procedural blocks for combinational logic. It appears frequently in hardware design interviews because the difference affects both code correctness and synthesis behavior.

To answer this well, you need to understand how SystemVerilog treats sensitivity lists, handles latch inference, and enforces blocking vs. non-blocking assignments. The two constructs look similar on the surface, but they differ in their guarantees about completeness and simulation semantics—differences that can lead to bugs that are hard to catch without careful analysis.

• Sensitivity list completeness and implicit vs. explicit nets
• Latch inference rules and undriven variable detection
• Blocking vs. non-blocking assignment semantics in combinational contexts
• Synthesis implications and simulation-to-hardware fidelity