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A child and the parent is a easy quant interview question on verification in System Verilog.
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This is an easy SystemVerilog question that tests your grasp of class inheritance and method resolution in object-oriented hardware verification. It targets candidates who need to work with testbench hierarchies where derived classes extend or override parent functionality.
The question probes whether you know the specific keyword syntax for disambiguating and explicitly calling a parent class method from within a derived class context. This is a foundational OOP concept in SystemVerilog that appears frequently in real testbench code, especially when a derived class needs to invoke parent setup, cleanup, or helper tasks before or after its own logic.
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