Same line, different time.

What this cache-line contention concurrency question tests

This is a hard concurrency question that quant firms ask to assess whether candidates understand the hardware realities underlying multi-threaded performance. It probes knowledge of how CPU caches work and why naive parallelism often fails to deliver speedup on shared-memory systems.

The question targets the gap between theoretical concurrency and actual performance: two threads working on logically independent data can still serialize at the hardware level if that data happens to share a cache line. Solving it requires you to name the phenomenon, explain the mechanism (cache coherence protocols and invalidation), and understand why this matters for latency-sensitive code.

• Cache line size and alignment
• Cache coherence protocols (MESI, MOESI)
• False sharing vs. true sharing
• Performance implications of memory layout