PML4

What this page-table architecture interview question tests

This is an easy operating-systems question that quant firms use to assess whether candidates understand the relationship between address-space layout, paging structures, and hardware constraints. It rewards clear thinking about how virtual memory is translated to physical memory.

To work through problems like this, you need to understand how a multi-level paging scheme partitions a 64-bit virtual address, how page size determines the structure of each level, and how the remaining address bits constrain the number of entries at each table. The question tests whether you can reason from first principles about memory hierarchy rather than memorize an answer.

• Virtual and physical address translation
• Address-space partitioning and bit allocation
• Page size and indexing constraints
• Multi-level page-table design tradeoffs