PML?

What this hard operating-systems question tests

This is a hard operating-systems question about page-table architecture and memory management on 64-bit systems. It probes your understanding of how virtual-address translation works when page tables themselves must fit within the physical memory constraints of a single page.

To solve it, you need to reason about the relationship between address-space width, page size, and the branching factor of a multi-level page-table hierarchy. The key insight is that each level of indirection must itself reside in a single page, which limits how many entries each table can hold. Quant firms and systems-focused roles ask questions like this to verify that candidates can work backwards from hardware constraints to derive architectural limits.

• Virtual-address translation and page-table walk mechanics
• Paging granularity and address-space partitioning
• Trade-offs between hierarchy depth and table density