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Random constraints is a cooked quant interview question on verification in System Verilog.
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This question tests your ability to correctly declare and apply randomization constraints in a SystemVerilog testbench class. It is representative of the kind of practical verification knowledge that hardware design teams expect, particularly when you need to generate valid stimulus that respects both functional and alignment requirements.
The scenario requires you to constrain a randomly generated address field to fall within a specific memory region and satisfy a byte-alignment property simultaneously. This is a common pattern in assertion-based verification and constrained-random testing (CRT). The challenge is understanding SystemVerilog's constraint syntax, the order in which constraints are evaluated, and how to express both range and modular arithmetic conditions cleanly.