Assertion passing but incorrect values?

Debugging SystemVerilog assertions in a fetch-unit design

This medium-difficulty SystemVerilog question tests your ability to reason about assertion semantics and temporal logic in the context of control-flow hardware. It's the kind of debugging exercise that appears in design-verification interviews at firms that build or verify processor pipelines and fetch logic.

The core challenge is understanding the difference between what an assertion syntactically claims to check and what it actually observes during simulation. Assertions can pass for the wrong reasons—or equivalently, can reveal correct behavior while masking subtle bugs in the specification itself. Working through these scenarios requires careful attention to timing, enable conditions, and the order in which signals are sampled relative to clock edges.

• Immediate vs. deferred assertions and sampling semantics
• Conditional property evaluation and enable-signal placement
• PC arithmetic and pc+2 increment logic verification
• Interaction between branch_en, pc_en, and assertion triggering