Which assertion type?

Choosing the right SystemVerilog assertion type for design verification

This easy SystemVerilog question tests whether you understand the distinction between immediate and concurrent assertions in SystemVerilog. It appears frequently in design-verification interviews because it's foundational: picking the wrong assertion type leads to either missed bugs or false failures in simulation.

The question presents two realistic design constraints: one that must never occur at any point, and another that describes a precise temporal sequence. Each requires a different assertion mechanism. The key insight is recognizing whether you're checking a combinational property (something that must hold right now) or a sequential property (something that must unfold over cycles in a specific pattern).

• Immediate vs. concurrent assertions
• Temporal reasoning in SystemVerilog
• When to use simple constraints vs. property sequences