4-bit ALU Verification

Developing a test strategy for 4-bit ALU verification in SystemVerilog

This easy-level verification problem tests your ability to design a structured test plan for a small but complete design. You are given a 4-bit ALU with eight operations (add, subtract, bitwise AND, OR, XOR, NOT, and two pass-through modes) and eleven distinct requirements covering functional correctness and flag outputs. The challenge is not the complexity of any single operation, but deciding how much and what kind of testing each requirement actually needs.

The core skill here is distinguishing between exhaustive coverage (sometimes necessary, often wasteful) and sufficient coverage. For a 4-bit ALU with two 4-bit inputs and a 3-bit opcode, brute-force enumeration is computationally feasible, but that is only one valid approach. You must reason about which operations benefit from corner-case targeting (such as carry and borrow logic) versus which can be verified by sampling or by understanding the design's symmetry. Your answer should clearly map test cases to requirements and justify your choice of test count.

• Exhaustive vs. directed test selection
• Coverage metrics for arithmetic and logic operations
• Carry, borrow, and flag verification
• Test plan organization and traceability to requirements