Variables vs Signals in Simulation

Understanding variables and signals in VHDL simulation

This is a hard conceptual question on VHDL design and verification that tests whether you understand the fundamental semantic difference between variables and signals, and when each serves a practical purpose in simulation. It appears frequently in design-verification interviews where candidates are expected to reason clearly about timing, concurrency, and the execution model.

To answer well, you need to consider how variables and signals behave differently under the VHDL delta-cycle execution model, what trade-offs exist when writing testbenches versus synthesisable RTL code, and whether the choice affects simulation performance, code clarity, or correctness. Interviewers are looking for evidence that you understand not just the syntactic rules, but the why behind them.

• Delta cycles and the VHDL simulation kernel
• Immediate versus delayed assignment semantics
• Synthesisability constraints in RTL versus testbench flexibility
• Race conditions and non-determinism in concurrent contexts
• Simulation speed and waveform visibility