Rand(c)?

Understanding rand and randc variable modifiers in SystemVerilog

This is an easy verification question that tests knowledge of SystemVerilog's randomization features. It appears frequently in interviews at firms that build simulation testbenches and constrained-random verification environments, where understanding the subtle differences between randomization modes is essential to writing effective testbenches.

The question probes whether you grasp how SystemVerilog generates random values across multiple stimulus iterations, and when to choose each approach. The distinction matters for test coverage, convergence speed, and the kinds of value sequences your stimulus generator produces. A clear answer should explain the underlying behavior of each modifier and identify practical scenarios where one is preferred over the other.

• Unconstrained vs. cyclic randomization patterns
• Testbench stimulus generation and coverage
• SystemVerilog constraint and randomize() semantics