Smaller, faster, better

What this FPGA synthesis and timing question tests

This is an easy question on practical FPGA design trade-offs and how RTL constructs map to hardware resources. It rewards understanding the difference between what simulates correctly and what synthesizes efficiently—a critical distinction in hardware design.

The question probes whether you can diagnose a timing and area problem by reasoning about how your choice of RTL construct (case statement vs. alternative) will be implemented after synthesis. On FPGAs, the synthesizer's interpretation of combinational logic directly affects both the depth of the critical path and the number of LUTs consumed. A strong answer identifies the specific construct that the synthesis tool can optimize for lookup-table-style logic and explains why it reduces both latency and resource usage.

• Combinational vs. registered logic trade-offs
• How FPGA synthesis maps RTL to LUT and routing resources
• Read-only memories and their efficient implementation
• Critical path timing in synthesized designs