Understanding Hold Violations

Diagnosing hold-time violations in synchronous digital circuits

This is a hard static timing analysis (STA) question that tests whether you can correctly apply hold-time constraints to multi-path register-to-register logic. Hold violations are often more subtle than setup violations because they depend on the minimum delay through a path and the relative timing of launch and capture clocks on the same or adjacent cycles.

To solve problems like this, you must compute the actual data arrival time at the capture register and compare it against the hold requirement window. The key insight is that hold time is checked at the clock edge of the capture register, and data must not arrive too early — that is, before the register has released its previous value. Strong candidates set up the timing inequality systematically for each path, track which paths operate on the same or overlapping clock cycles, and identify violations by comparing minimum data delay against the hold margin.

• Clock-to-Q propagation delay from the launch register
• Minimum combinational logic delay on the data path
• Hold time requirement at the capture register
• Clock skew and relative arrival times between launch and capture clocks
• Single-cycle vs. multi-cycle path behaviour