Wrong bet

What this clock-domain crossing synchronization question tests

This is a medium-difficulty hardware design question that probes understanding of metastability and safe pointer comparison across asynchronous clock domains. It is the kind of problem that appears in SystemVerilog design interviews at firms building high-performance digital systems, where FIFO reliability directly impacts system correctness.

The question challenges candidates to reason about why a naive synchronization strategy—passing each bit of a binary pointer through a standard two-flop synchronizer independently—can fail, even after the metastability window has passed. The issue lies in the relationship between the data being synchronized and the guarantees that basic synchronizer primitives provide. Solving this requires understanding both the hazards of crossing clock domains and the subtle difference between synchronizing individual bits versus synchronizing multi-bit quantities with a specific structure.

• Metastability and synchronizer design
• Gray code encoding for multi-bit synchronization
• Pointer comparison in dual-clock FIFOs
• Bit-slipping and coherency across clock domains