X Indexed Y Tagged 1

What this cache architecture question tests

This is an easy computer-architecture question that probes understanding of the tradeoffs between different cache indexing and tagging schemes. It asks candidates to reason about the practical limitations of one common design choice and why systems engineers avoid it in certain scenarios.

To answer questions like this, you need to understand how physical and virtual addressing interact with cache lookup. Specifically, the question targets the performance or correctness penalty that arises when both the cache index and tag are derived from physical memory addresses rather than virtual ones. Strong answers identify the specific bottleneck or constraint that makes this design choice unattractive, and can explain why alternative architectures (such as virtually indexed, physically tagged) are often preferred.

• Virtual vs. physical addressing in cache design
• Address translation latency and the critical path
• Cache coherency and aliasing concerns