X Indexed Y Tagged 3

Understanding virtually indexed physically tagged cache design tradeoffs

This question tests your grasp of cache architecture fundamentals—specifically, the design choices that balance speed, correctness, and hardware complexity. It asks you to reason about why a hybrid indexing and tagging scheme might be preferable to its pure alternatives, and what practical problem it solves.

To answer well, you need to understand how virtual and physical addresses flow through the cache pipeline, when address translation happens, and what aliasing or coherence issues arise under each scheme. The question rewards clear thinking about the temporal ordering of cache operations and the cost of virtual-to-physical translation in the critical path.

• Virtual vs. physical address spaces and their timing in the pipeline
• Cache aliasing and coherence challenges in virtually-tagged designs
• Translation lookaside buffer (TLB) latency and when it blocks cache lookup
• Comparative tradeoffs between index and tag schemes