X Indexed Y Tagged 2

Understanding virtually indexed virtually tagged cache design tradeoffs

This is a hard computer architecture question that tests your grasp of cache indexing and tagging schemes—a core concern in processor design. It asks you to reason about the fundamental performance and correctness implications of one particular cache organization strategy, comparing it against alternatives like physically indexed caches.

To answer well, you need to understand how virtual and physical address translation interacts with cache lookup, and where that interaction creates practical problems. The question rewards candidates who can identify not just what goes wrong, but why it matters enough for hardware designers to often choose a different approach. You should be prepared to explain the mechanism behind the disadvantage and discuss how it affects real system behavior.

• Virtual vs. physical indexing and tagging trade-offs
• Address translation latency and the critical path
• Correctness issues in multi-process and multi-core environments
• Cache hierarchy design constraints