Don't touch me

Understanding dont_touch constraints in synthesis and static timing analysis

This is an easy question on synthesis and STA that tests whether candidates understand how tool directives apply across a design hierarchy. It probes a common pitfall: confusing the scope and effect of compile-time constraints when the same module appears in multiple contexts with different performance requirements.

The question rewards knowledge of how set_dont_touch works, why designers use it, and the distinction between applying constraints at the module definition versus the instance level. It also touches on the tension between preserving module integrity and optimising specific instances for their local timing context.

• Hierarchy, scope, and instance-level vs. definition-level constraints
• Synthesis tool optimisation directives and their precedence
• Timing-driven synthesis and the role of SDC (Synopsys Design Constraints)
• Trade-offs between reusability and performance tuning