Speedup

Understanding instruction pipelining and throughput

This medium-difficulty computer-architecture question tests your grasp of how instruction pipelining improves processor throughput. Modern processors break instruction execution into discrete stages—fetch, decode, execute, and write-back—and pipeline them so multiple instructions progress through different stages simultaneously, rather than one instruction completing all four stages before the next begins.

The question asks you to calculate how many instructions finish in a given time window when the pipeline operates at full capacity. This requires understanding the difference between latency (time for one instruction to traverse the entire pipeline) and throughput (instructions completed per unit time). A key insight is recognizing that once the pipeline fills, one instruction completes per cycle, despite each stage taking multiple nanoseconds in the non-pipelined case.

• Pipeline latency vs. throughput
• Fill time and steady-state operation
• Clock cycles vs. nanoseconds in pipelined architectures