Cache me if you can!

What this cache-performance interview question tests

This is a medium-difficulty computer architecture question that assesses your understanding of cache locality and how data access patterns interact with cache geometry. It's common at trading firms and systems-oriented companies where performance matters, and candidates must reason about real hardware constraints rather than just algorithmic complexity.

The question asks you to predict cache misses for two different implementations of the same logical operation. To solve it, you need to understand how a direct-mapped cache maps memory addresses to cache blocks, how the block size affects alignment, and why the order in which you access memory can dramatically change miss rates. The comparison between function A and function B rewards candidates who recognize that not all "clever" rewrites actually improve performance—sometimes sequential access or better spatial locality wins.

• Direct-mapped cache address mapping and block offset extraction
• Cache hit vs. miss conditions under cold-start assumptions
• Spatial and temporal locality in nested loops
• How stride and access order affect eviction and reuse