Which-Way Associativity?

Understanding cache associativity in computer architecture

This easy question tests your grasp of cache memory organisation, specifically the trade-offs between different mapping strategies. Cache associativity determines how flexibly a memory address can be stored and retrieved within the cache hierarchy—a fundamental concept for understanding modern CPU performance.

When designing or reasoning about processor caches, engineers choose between fully associative, set-associative, and direct-mapped approaches. Each variant balances hardware complexity, lookup speed, and the likelihood of cache conflicts. This question asks you to distinguish the practical, widely-used forms from less common or theoretical alternatives.

• Direct-mapped cache organisation
• Set-associative caching (n-way)
• Fully associative caches
• Trade-offs between flexibility and implementation cost