How big are the lines?

What this computer-architecture interview question tests

This is a foundational question about CPU cache design that appears in systems and low-latency trading interviews. It tests whether a candidate understands the physical and logical constraints that shape modern processor memory hierarchies, and can reason about why those constraints matter for performance.

The question sits at the intersection of hardware specification and software intuition. Candidates should know the typical value for contemporary systems and be able to explain the trade-offs behind it—why that size balances spatial locality, bandwidth efficiency, and on-chip area. Interviewers often follow up by asking how cache-line size affects data layout, false sharing in multi-threaded code, or prefetching strategy.

• Spatial locality and memory access patterns
• Cache hierarchy and coherence protocols
• Alignment and padding in performance-critical code
• False sharing in concurrent systems