How big is it?

What this computer-architecture cache-design question tests

This is an easy question on cache organisation and memory hierarchy fundamentals. It assesses whether you understand how physical cache parameters—total size, line width, and associativity—interact to determine the layout of a real cache.

To solve problems like this, you need to work through the arithmetic of cache geometry: how many lines fit in the total capacity, how associativity divides those lines into sets, and which bits of a memory address map to each component (tag, set index, offset). These calculations are foundational for reasoning about cache behaviour, miss rates, and memory-system performance tuning.

• Cache line size and byte offset bits
• Set associativity and line-to-set mapping
• Address decomposition (tag, index, offset)
• Total capacity arithmetic