It's massive.

What this computer-architecture cache-sizing question tests

This is an easy factual question about modern CPU design that appears in screening interviews at quantitative firms. It tests whether you have concrete familiarity with the hardware layer beneath your code — specifically, the memory hierarchy that governs latency and throughput in performance-critical systems.

In low-latency trading and systems programming, understanding cache behaviour is not optional. Knowing typical L1 cache sizes, access latencies, and line widths helps you reason about data layout, prefetching, and false-sharing effects that can make or break a microsecond-scale implementation.

• CPU cache hierarchy: L1, L2, L3, and main memory
• Cache line size and alignment
• Latency and bandwidth trade-offs across memory levels
• How cache constraints shape algorithm design