Space the cache

What this cache-addressing interview question tests

This is an easy computer-architecture question that probes your understanding of how physical memory maps onto cache hardware. It's the kind of foundational problem that operating-systems and systems-programming interviews use to verify you can reason about cache geometry: the relationships between cache size, line size, associativity, and address layout.

To solve problems like this, you need to understand what each architectural parameter controls—specifically, how cache lines are sized and how the CPU uses bits from a memory address to locate data within the cache hierarchy. The question rewards careful, methodical calculation over intuition.

• Cache line size and byte-addressing
• Tag, index, and offset fields in a cache address
• How set associativity affects address decomposition
• Powers of two and bit-width relationships