Map the cache

What this cache-mapping interview question tests

This is a medium-difficulty systems question that probes whether you understand the layered relationship between physical memory, cache hardware, and address translation. It requires you to reason backwards from cache parameters (line size, total capacity, associativity) to derive the bit-width of address fields.

To solve problems like this, you need to know how a direct-mapped cache partitions a memory address into tag, set-index, and block-offset fields. The question rewards careful arithmetic and clear understanding of what each field represents and why its width matters for hardware correctness.

• Cache line size and block-offset bits
• Set associativity and indexing
• Total cache capacity and set count
• Address field decomposition in direct-mapped caches