Map the cache, again

What this cache-mapping interview question tests

This is a medium-difficulty computer architecture question that appears in systems and operating-systems interviews. It probes your understanding of how physical memory maps onto cache hardware—specifically, the relationship between cache size, line size, and associativity when determining address bit allocation.

To solve problems like this, you need to work through the hierarchy of cache parameters: total cache capacity, the size of each cache line, and the associativity model. From these constraints, you can derive how many address bits are needed to locate a specific line in the cache. The question rewards clarity in distinguishing between offset bits, index bits, and tag bits in a memory address.

• Cache line size and byte-offset encoding
• Set indexing in associative caches
• Address bit partitioning in cache hierarchies
• Fully associative vs. set-associative cache structures